An EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used as an electrically writable and erasable non-volatile semiconductor memory device. These memory devices which have been widely used at present and are represented by a flash memory include a conductive floating gate electrode or a trap insulating film surrounded by an oxide film under a gate electrode of a MISFET, and are configured to store the charge accumulation state of the floating gate electrode or the trap insulating film as memory information and read the memory information as a threshold of the transistor. This trap insulating film indicates an insulating film which is capable of accumulating a charge, and examples thereof include a silicon nitride film and the like. The threshold of the MISFET is shifted by injecting or releasing the charge into or from such a charge accumulating region, thereby operating the MISFET as the memory element. Examples of the flash memory include a split gate cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. Such a memory uses a silicon nitride film as the charge accumulating region, and is thus advantageous in terms of discretely accumulating the charge and having excellent reliability of data retention as compared to the conductive floating gate film. In addition, since the memory has the excellent reliability of data retention, it is possible to reduce the thickness of oxide films above and below the silicon nitride film, and thus a voltage required for write and erase operations can be lowered.
Further, a memory cell includes a control gate electrode (selection gate electrode) which is formed on a semiconductor substrate via a first gate insulating film, a memory gate electrode which is formed on the semiconductor substrate via a second gate insulating film including the charge accumulating region, and a pair of semiconductor regions (source region and drain region) formed in a surface of the semiconductor substrate so as to sandwich the control gate electrode and the memory gate electrode.
Further, Japanese Patent Application Laid-Open Publication No. 2006-41354 (Patent Document 1) discloses a memory cell in which a convex-shaped active region is formed on a surface of a semiconductor substrate and a control gate electrode and a memory gate electrode are arranged so as to be laid across the convex-shaped active region.
In addition, Japanese Patent Application Laid-Open Publication No. 2013-504221 (Patent Document 2) discloses a Fin-FET non-volatile memory cell including a word line arranged so as to be laid across a fin shaped member, a floating gate positioned immediately adjacent to the word line and capacitively coupled to a side surface of the fin shaped member, and a coupling gate positioned above the floating gate and capacitively coupled to the floating gate.
In addition, US Patent Application Publication No. 2014/0077303 (Patent Document 3) discloses a fin transistor that includes different fin widths.